1. Technical Field
The present invention relates to a method and system for sharing data among cache memories in general and, in particular, to a method and system for sharing data among cache memories within a multiprocessor data-processing system. Still more particularly, the present invention relates to a method and system for speculatively sourcing data for a cache memory within a multiprocessor data-processing system.
2. Description of the Prior Art
In a symmetric multiprocessor (SMP) data-processing system, all of the processing units are generally identical; that is, they all utilize a common set or subset of instructions and protocols to operate and, generally, have the same architecture. Each processing unit includes a processor core having multiple registers and execution units for carrying out program instructions. Each processing unit also may have one or more primary caches (i.e., level one or L1 caches), such as an instruction cache and/or a data cache, which are implemented utilizing high-speed memories. In addition, each processing unit also may include additional caches, typically referred to as a secondary cache (i.e., level two or L2 cache) for supporting the primary caches such as those mentioned above.
Under an SMP environment, the transfer of data from one processing unit to another processing unit on a system bus without going through a system memory is referred to as an intervention. An intervention protocol improves system performance by reducing the number of cases in which the system memory must be accessed in order to satisfy a read or read-with-intent-to-modify (RWITM) request by any one of the processing units within the system.
Broadly speaking, when there is an outstanding read/RWITM request by a processing unit, any one of the other processing units, attached to the system bus, that possesses the requested data within its cache(s) can source the data to the requesting processing unit. Under the traditional intervention protocol, the processing unit having the data residing in its cache will wait for a "combined" response from all processing units within the system before issuing a data bus request to source the data from its cache(s).
At the same time, SMP buses also have a "retry" mechanism, and any read/RWITM request that could be satisfied by an intervention could also be interrupted by a "retry" from any one of the processing units on the system bus. If one processing unit responds with an intervention while another processing unit responds with a "retry," under a well- established rule, the retry response automatically overrules the intervention response. As a result, if there is an outstanding retry request by any one of the processing units on the system bus, the processing unit that contains the data will not issue a data bus request.
Consequently, it would be desirable to provide an improved sourcing scheme in which intervention data will be sourced in such a way that is less influenced by the "retries" from any of the processing units within the multiprocessor data-processing system.